1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, this invention relates to a multi-layered structure of a semiconductor device which has an interconnection layer and a layer formed thereon to suppress light reflection.
2. Description of the Related Art
Conventional semiconductors are fabricated having interconnections formed between the various regions of the semiconductor. These interconnections are typically fabricated from conductive material deposited on the semiconductor substrate during metallization process and effectively form bonding areas between the various substrates. Depending on the type of conductive material used for the interconnection, various electrical and mechanical characteristics are imparted to the semiconductor, such as reflectance, electromigration (EM), stress migration (SM), and interconnection resistance.
Due to the recent high integration of semiconductor devices, there is a demand to reduce the interconnection widths formed during the fabrication of semiconductors to 0.5 .mu.m or narrower. Interconnection miniaturization, however presents certain difficulties in the operational performance of highly integrated semiconductor devices. Such problems include the deterioration of the electromigration performance and stress migration performance, an increase in interconnection resistance and a reduction in precision of photolithographic patterning, caused by the reflection of exposure light (called "halation") at the surface of the interconnection layer. Semiconductor devices which will overcome those problems are therefore widely sought after. The "electromigration" is a phenomenon wherein the interconnection is disconnected by the migration of aluminum atoms due to the flow of electrons. The "stress migration" is the disconnection of the interconnection caused by thermal stress.
FIG. 1 shows the cross section of a semiconductor device having a conventional multi-layered structure. A silicon oxide (SiO.sub.2) film 101 is formed 200 nm thick on a single crystal silicon substrate 100 by the chemical vapor deposition (CVD) method. An aluminum-silicon-copper alloy layer 102 (Al--Si (1% by weight)-Cu (0.5% by weight)) is deposited 500 nm thick on the SiO.sub.2 layer 101 by the magnetron sputtering method. A titanium nitride (TiN) layer 103 is formed 20 nm thick on the alloy layer 102 by the reactive sputtering method using titanium (Ti) as a target and a gas mixture consisting of argon and nitrogen as a sputtering gas. According to this reactive sputtering method, titanium sputtered from the target is deposited on the alloy layer 102 while reacting with the nitrogen in the sputtering gas, thus yielding the TiN layer 103. The two layers 102 and 103 form an interconnection layer 104 which is to be patterned by photolithography. The TiN layer 103 serves to suppress reflection of light (e.g., ultraviolet rays) exposed at the surface of the interconnection layer 104 during the photolithography to thereby improve the patterning precision. Such a reflection suppressing layer is generally called "cap metal".
The influence of the light exposed on the surface of the interconnection layer 104 will now be discussed with reference to FIG. 2. The first step of the photolithography is to form a resist 105 (e.g., a positive photoresist) on the interconnection layer 104 (step 1). Light passing through a mask (not shown) is irradiated on a specific area of the resist 105. If no cap metal exists on the surface of the interconnection layer 104, which is in contact with the resist 105 (namely, if the reflectance of the surface of the interconnection layer 104 is high), or if there are undulations on the interconnection layer 104 corresponding to those of the silicon substrate 100, most of the exposure light would be reflected at the surface of the interconnection layer 104 and would be irradiated on a resist 105a around the specific area. This results in inaccurate patterning of the hardened resist that will remain after removal of the unnecessary resist. As a result, the actual size or shape (W1) of the gap between interconnection patterns obtained after etching differs from the desired size or shape (W2).
To address this problem, the cap-metal layer 103 consisting of low-reflectance TiN is formed on the alloy layer 102 in the conventional interconnection layer 104 shown in FIG. 1. If the wavelength of light for measuring the reflectance is 365 nm, which is the same as the wavelength of normal exposure light used in the photolithography, the reflectance of the interconnection layer 104 having the TiN layer 103 is reduced to about 30%, which is considerably lower than that of the interconnection layer that consists only of the alloy layer 102.
While the conventional interconnection layer 104 having the TiN layer 103 is satisfactory in suppressing halation, it does not sufficiently achieve the currently demanded levels of the other performances like the EM immunity and SM immunity.